This invention relates generally to the design of integrated circuits and more particularly to the automated design of integrated circuits by behavioral synthesis.
Over the past several decades, integrated circuits (ICs) have become an integral part of modern electrical devices. Rather than using off the shelf components, it is often desirable to use custom or semi-custom ICs. To permit easier circuit design of custom or semi-custom ICs to fulfill specific performance constraints or circuit requirements and to aid in circuit fabrication, automated systems for design and manufacturing have been developed.
One type of computer aided design (CAD) system is known as a "behavioral synthesis system." With such a system, the inputs, outputs and other circuit parameters are input into a computer using a hardware description language (HDL). Behavioral synthesis software then designs a circuit meeting these parameters.
A typical integrated circuit design and manufacturing process using behavioral synthesis beains with certain performance or structural constraints. A description of these constraints is made using an HDL such as VHDL or VERILOG which are commercially available behavioral synthesis languages. This HDL can be processed to form a "net" or "netlist" specifying components and their interconnections which meet the circuit constraints. However, the actual placement plan of components on wafers and the topography of the wiring connections is reserved for a subsequent "layout" stage.
Clock signals are used within integrated circuits to synchronize the operation of the various components. This timing is crucial in digital circuits since the combination of logic states at specified times of various components defines the function of a digital circuit. However, the routing of the connections between components can cause a disparity between clock signals at a particular time at different components within a circuit. This disparity is called clock skew and is defined in terms of signal delays between the input of the clock signal and its reception at the components in question.
Components using a single clock are represented as a subnet of the netlist called a "clocknet." A corresponding "clock tree" is a description of not only the components of the clocknet but also their manner of connection. Skew and driveability are particularly relevant for large clock circuits represented by correspondingly large clock trees. Driveabilty is directly related to the number of buffers (intermediate components), their collective capacitance, and the resistances of wires connecting the buffers. It is generally difficult to drive a large clock tree using a single buffer. Such a large clock tree may have large clock rise times or "ramp delays" on the order of nano-seconds and hence generate distorted clock signals.
A conventional method 10 for fabricating an integrated circuit is outlined in a flowchart in FIG. 1 beginning at a step 12. In a step 14, a set of circuit specifications is developed. Generally, these specifications can include the overall integrated circuit performance and also specific size and placement characteristics of components on a chip. In particular, maximum clock skew, minimum ramp delay, minimum driveability, number of buffers and total wire length may be specified.
A circuit designer will create a description of these specifications in a step 16 using a hardware description language (HDL). Common hardware description languages include VHDL and VERILOG although any suitable language can be used. This description of the specifications is then used in a step 18 to synthesize a netlist which specifies which components will be connected but does not specify the precise wiring topography. Components described by the netlist will form a circuit satisfying the circuit specifications. Those components which will share a common clock will be part of a clocknet which in turn is part of "netlist" or "net". At this stage, a conventional method would generally verify in a step 20 the behavior and functionality of the circuit described by the netlist.
Further referring to the conventional process of FIG. 1, the circuit designer transfers transforms the netlist description into a layout of the integrated circuit in a step 24. This layout step 24 determines the actual physical placement of components on the integrated circuit die or chip to form an array of gates or standard cells. The routing of connections or wires between components is also determined in layout step 24. The output of step 24 is data that is often in Caltech Intermediate Format (C.I.F.).
The C.I.F data created in the step 24 is then processed a step 26 to create a set of integrated circuit masks. These masks are used in the fabrication the integrated circuit chip. It has the precise pattern used for forming the connections of components on the chip. These masks are typically generated on a machine equipped to read C.I.F. data. This C.I.F. data can be transferred to this machine through a hard disk, magnetic tape, a floppy disk, or other means. It is also possible for the mask generating machine to be part of or the same machine that synthesizes the netlist.
An integrated circuit is produced in a step 28. A conventional method of producing the circuit is to use the masks created in step 26 in a photolithography process. Once the chip itself has been fabricated, the integrated circuit on the die must have connections to external circuitry. This is generally accomplished by attaching bonding wires and/or lead frames to the integrated circuit. The circuit is then encapsulated in packaging materials such as plastic. The design and fabrication of the integrated circuit ends at a step 30.
The insertion of buffers into digital circuits to rectify clock skew has been proposed by Tsay in "Exact Zero Skew", IEEE-CAD, pp. 336-339, 1991. However, Tsay does not outline a specific method for buffer insertion to minimize clock skew or specify how to minimize the number of inserted buffers. Cho et al. have proposed an insertion method in "A Buffer Distribution Algorithm for High Speed Clock Routing," Proceedings of the 30th Design Automation Conference, pp. 537-543, 1993. However, they do not account for buffer delay, and they increase the overall length of wire connecting components.